1b69254de2
Replace the vendored runtime MLP in vcv/src/iml.hpp (DetRng + 3D-weight-store MLP + Dataset + IML) with a THIN, Rack-free adapter over the shared core: nisps::ml::MLPCore<nisps::ml::DynamicStorage> (8->[16,24,16]->16, the P2 dynamic case), nisps::Rng, and the core MLP's own FIFO dataset. Behaviour changes from the vendored approximation to core-exact firmware/WASM semantics. - MEMLNaut.cpp: staged/pending weight buffers and patch JSON now use the core's flat [weights..][biases..] vector (nisps::IML<float>::Weights); patch version bumped to 3. Double-buffer / single-writer threading discipline unchanged. - New ctest tests/cpp/test_vcv_iml_parity.cpp: seeded train/infer/move_weights session through the adapter is memcmp-equal to a bare MLPCore<DynamicStorage>. - Docs: vcv-module.md delta #5 marked CLOSED (2026-07-18); MAP.md vcv/ updated. Closes vcv-module.md delta #5. |
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| .. | ||
| _archive | ||
| plans | ||
| recon | ||
| aimmersive-clone-spec.md | ||
| backends-spec.md | ||
| dock-spec.md | ||
| engine-architecture.md | ||
| feedback-modes-port-spec.md | ||
| inputs-spec.md | ||
| MAIN.md | ||
| manifold-parity-features-spec.md | ||
| slp-workshop-firmware.md | ||
| useq-cv-protocol.md | ||
| vcv-module.md | ||