memlnaut-nisps/nisps
monkey-w1n5t0n 96737a3d42 refactor(engines): extract the shared sequencer machinery
Phase 3 (L8). Pure statement-for-statement relocation into
dsp/ratio_seq.hpp, dsp/seq_clock.hpp and core/event_queue.hpp.

AUDIT CORRECTION: L8 says "breakor and elysiamorf duplicate ratio_seq". That is
false — ElysiamorfEngine has no ratio_seq at all; it triggers continuously via
FM operators. The real duplicate pair is BreakOrEngine and MEMLCeliumEngine,
whose copies are byte-for-byte identical. Elysiamorf did share the clock and
event-queue machinery, so it uses those. memlcelium now includes the shared
ratio_seq too, which is what actually closes this finding.

Deliberately NOT folded into core/ring_buffer.hpp: RingBuffer is an
atomics-based cross-core SPSC channel (its header says so), whereas the engines'
event queue is produced and drained on one thread. Reusing it would have meant
paying for atomics to serve a single-threaded FIFO. The distinction is now
recorded in MAP.md so the next audit does not read them as duplicates.

Bit-exactness: verified the MIDI-clock tick and bar-phasor tick preserve the
original operation order with no floating-point re-association, and that
EventQueue keeps the original `% N` indexing rather than adopting RingBuffer's
bitmask. The golden suite (nisps_golden_tests) and the native<->WASM parity blob
both pass unchanged — they are the check, and they were not re-baselined.
2026-07-21 14:02:23 +02:00
..
core refactor(engines): extract the shared sequencer machinery 2026-07-21 14:02:23 +02:00
dsp refactor(engines): extract the shared sequencer machinery 2026-07-21 14:02:23 +02:00
engines refactor(engines): extract the shared sequencer machinery 2026-07-21 14:02:23 +02:00
midi/generated feat(midi-devices): canonical external-synth CC templates + dual codegen 2026-06-28 20:03:17 +02:00
ml fix(ml): one named example capacity; train() and trainAsync() no longer diverge 2026-07-21 13:22:38 +02:00
modes refactor(codegen): codegen owns mode identity, per-mode schemas and net dims 2026-07-21 14:02:23 +02:00
pipeline feat(pipeline)!: P4 core — input/output chains + curve catalog in nisps/ 2026-07-18 11:52:53 +02:00
wasm fix(ml): one named example capacity; train() and trainAsync() no longer diverge 2026-07-21 13:22:38 +02:00
.gitignore feat: nisps/core foundation — perf, types, concepts, buffers, rng, math 2026-04-29 15:21:52 +03:00
CMakeLists.txt refactor(engines): extract the shared sequencer machinery 2026-07-21 14:02:23 +02:00